1. Field of the Invention
The present invention relates to a shift register for use in semiconductor memory devices and the like, and more particularly to an improved shift register having both a mode whereby external commands are temporarily latched and a mode whereby the element functions as a counter for time measurement, and to a flash memory utilizing this shift register.
2. Description of the Related Art
In flash memories and other semiconductor memory devices, external commands instructing write, read, delete, or other operations are decoded, and corresponding command flags are stored in memory. Shift registers are provided for latching the decoded command flags.
In flash memories, it is necessary to apply erasing voltage to the memory transistor gates for a given period of time in order to erase the contents. An internal timer comprising a counter which measures the erase time is provided for this purpose.
However, latching shift registers and the shift registers which make up counters have the same circuit architecture, and, according to internal circuit operation theory, are not used simultaneously in some instances. Accordingly, the provision of both latching shift registers and counter shift registers as internal circuits makes the circuit architecture unnecessarily complex, and increases the degree of integration.